The multiplications by several integer constants is a frequent operation in many algorithms implemented in embedded systems, e.g., the evaluation of digital filters. Instead of using costly generic multipliers, circuit designers usually lean towards multiplierless implementations, where a series of bit shifts and additions/subtractions, which come at lesser cost, is used instead. Aiming at reducing the hardware cost, the problem of finding a multiplierless implementation with the least number of adders, for a set of given target constants, is known as a Multiple Constant Multiplication (MCM) problem and conjectured to be NP-Hard. Another important metric, used in practice, is the delay, which is directly correlated to the adder depth, i.e., the maximum number of cascaded adders. When the adder depth is limited a priori, the problem is called a Bounded MCM (BMCM).

With this work we first propose a new ILP model for MCM as a minimization problem, allowing for better versatility. We also demonstrate a limitation of the state-of-the-art MCM model, which misses optimal solutions in certain cases, and correct it within our model. We further extend our model to solve the BMCM problem by adding necessary constraints into the ILP model, avoiding any heavy precomputations and neutralizing the main performance bottleneck of a second model from the literature. Moreover, we combine the minimization of both adder depth and the adder count into one objective function, offering a new complete MCM model. Finally, we propose new symmetry breaking constraints, which significantly improve the resolution process.